The present invention relates to a method of generating an interface between circuit blocks in designing a large-scale semiconductor integrated circuit device by using circuit blocks, which are existing resources for designing a circuit such as IPs (Intellectual Properties).
To reduce the number of designing steps, the development of such a large-scale integrated circuit device as termed, e.g., “system LSI” using circuit blocks termed IPs (or IP cores), which are existing resources for designing a circuit, has been started recently. The circuit blocks have predetermined input/output interfaces (I/F) which are normally different from one circuit block to another. In incorporating such circuit blocks having different interfaces into one system, therefore, it is an important design issue how to adjust the I/F of the individual circuits blocks and thereby promote smooth signal transmission between the individual circuit blocks. For example, it is necessary to modify logics and timings for I/F adjustment in incorporating the circuit blocks into one system.
To meet the necessity, a designing operation has been performed conventionally by a designer who recognizes input/output logics and timings of the circuit blocks, fully understands the difference in I/F structure between the individual circuits blocks, and newly designs an interface circuit or the like required to incorporate the circuit blocks such that the difference in I/F structure between the individual circuit blocks is absorbed and the connecting states between the individual circuit blocks are retained.
As a system LSI to be designed has been scaled up increasingly in recent years, however, the number of circuit blocks to be incorporated into the system LSI has also been increased exponentially. If an adjustment between the individual circuits is performed manually, an enormous amount of designing operation should be performed. In other words, it has been becoming difficult to efficiently design a large-scale integrated circuit device such as a system LSI by a conventional designing method which depends only on the skills of the designer.
On the other hand, there has been known such technology as follows which focuses attention on circuit behaviors such as the attributes and timings of signals and generates a new circuit from the circuit behaviors.
For example, Japanese Unexamined Patent Publication No. HEI 6-32972 discloses technology for generating a new hardware description language from a timing chart and the attributes of signals.
Japanese Unexamined Patent Publication No. HEI 7-253998 discloses technology for synthesizing, by using a truth table, behavioral descriptions of two or more logic circuits newly generated and thereby producing a new, complete circuit behavioral description.
Japanese Unexamined Patent Publication No. HEI 9-91355 discloses technology for generating circuit data, expected value data, timing data, or the like based on operational data, performing simulation, and automatically generating a new logic circuit.
In view of the foregoing, there can be considered the generation of a circuit for absorbing a difference in I/F structure between the circuit blocks by using the conventional methods of automatically generating circuits mentioned above.
Although the technology disclosed in the foregoing conventional publications allows generation of a new circuit block independent of the circuit blocks, the matter of how to smoothly retain the connecting states between the individual blocks remains to be solved. With the conventional technologies, it is difficult to generate an interface circuit considering a difference in I/F structure between the individual circuit blocks in the design of an integrated circuit device using circuit blocks which are existing resources.